Chopped charge pump

ABSTRACT

A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one of each pair to provide up current pulses and the other of each pair to provide down current pulses and switching on in a second phase the other of each pair to provide up current pulses and the one of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

RELATED APPLICATIONS

This application claims priority of U.S. Provisional Application No.60/483,411 filed Jun. 27, 2003 and U.S. Provisional Application No.60/544,439, filed Feb. 14, 2004, both incorporated by reference herein.

FIELD OF THE INVENTION

This invention relates generally to a charge pump and a phase frequencydetector (PFD) typically employed in a phase lock loop (PLL) and moreparticularly to an improved chopped charge pump which generates matchingcurrent up and down pulses and an improved PFD which provides matched upand down pulse widths.

BACKGROUND OF THE INVENTION

PLL synthesizers typically include a PFD which compares the inputreference frequency to a sub-multiple of the output frequency (e.g.,divided by N with a digital divider). The PFD generates up and downpulses which are applied to the charge pump. A conventional tri-statePFD includes a pair of bi-stable devices (e.g., D-type flip-flops) andgating logic. Because there is mismatch in the clock-to-Q delay in theflip-flops as well as mismatch in the reset-to-Q delay, the up and downpulses have slightly mismatched pulse widths which leads to outputoffset error. Moreover, any mismatch in the propagation delays of thegating logic in the up and down paths between the PFD and the chargepump will cause an output offset which results in static phase error.

The current sources of the single-ended charge pump of conventional dualbandwidth PLL synthesizers typically utilize different types of devicesfor the pump up and pump down current sources in the charge pump, e.g.,a PMOS device for up current pulses and an NMOS device for down current.Typically, the matching between the currents from the two differentdevices is no better than five percent. The result is mismatched up anddown current pulse magnitudes, that the charge pump generates. The PLLstructure that is commonly used in conventional synthesizers is a closedloop feedback system with two integrators in the forward path. Hence thePLL synthesizer will reach equilibrium with whatever static phase errorthe PLL synthesizer needs between the PFD inputs to ensure DC balance atthe loop filter node connected to the charge pump output. The DC oraverage value of the static phase error will be the amount required tocancel out the excess charge delivered to the loop filter due to themismatch. For example, a mismatch of 5% with a 3 ns minimum PFD turn-ontime would result in a phase skew of about 150 ps between the PFDinputs. In this example, if the RF output frequency is about 1850 MHz, aphase skew of 150 ps would corresponds to a static phase error of 100°at the output. Similarly, other imperfections in the PFD and/or theconventional single-ended charge pump, such as charge injection in thecharge pump switches and leakage current at the output, will result instatic phase error at the output of the PLL.

A prior art PLL circuit which attempts to reduce 1/f noise generated bythe charge pump is disclosed in U.S. Pat. No. 6,111,470, incorporatedherein by reference. The chopper stabilization technique as disclosed inthe '470 patent will reduce the 1/f noise component but the single-endeddesign is still prone to static phase error. The PLL of the '470 patentemploys a single-ended charge pump with only one output terminal whichrelies on a current mirror circuit to provide matching current up andcurrent down pulses. However, the inherent current losses in the currentmirror circuit, as well as the difference in propagation delay betweenthe direct path to the output and the path through the current mirror tothe output, results in a mismatch in the amplitude as well as timingbetween the actual up and down current pulses at the output. Also, sincethe elements being chopped are not identical (one device is a currentsource only and the other device is a current source and a currentmirror), the relatively high mismatch error being chopped will result ina high spur level at the chopping rate. Moreover, static phase errorresulting from the switch charge injection and output leakage will notbe reduced using the chopping technique and design as disclosed in the'470 patent.

A conventional differential charge pump may be employed in a PLL toimprove the matching of the current up and down pulses. A typicaldifferential charge pump attempts to match current sources of the sametype, e.g., PMOS to PMOS and NMOS to NMOS, rather than PMOS to NMOS asin the single-ended charge pump described above. A typical differentialcharge pump utilizes a pair of PMOS and NMOS devices to generate upcurrent pulses and another pair of PMOS and NMOS devices to generatedown current pulses. However, the PMOS and NMOS devices of adifferential charge pump have a residual mismatch due to processvariations. Leakage, headroom, and die area set a limit on how muchthese variations can be reduced. Hence, conventional differential chargepumps employed in a PLL do not provide completely matched current up andcurrent down pulses needed to eliminate static phase offset.

BRIEF SUMMARY OF THE INVENTION

It is therefore an object of this invention to provide an improvedchopped charge pump which provides matched up and down output currentpulses.

It is a further object of this invention to provide such an improvedchopped charged pump which eliminates static phase offset.

It is a further object of this invention to provide an improved choppedPFD which provides matched up and down pulse widths.

It is a further object of this invention to provide such an improvedchopped PFD with zero output offset.

It is a further object of this invention to provide an improved PLLwhich employs a chopped charge pump and a chopped PFD with zero staticphase offset.

This invention results from the realization that an innovative choppedcharge pump with matching current up and down pulses can be achievedwith first and second pairs of current sources and a switching circuitwhich switches, in a first phase, one of each pair of current sources toprovide up current pulses and the other of each pair to provide downcurrent pulses, then, in a second phase, switching the other of eachpair to provide up current pulses and the one of each pair to providedown current pulses to remove mismatch errors in the current response ofeach of the pairs of current sources and eliminate static phase offset.This invention results from the further realization that an improved PFDwith matching up and down pulses can be achieved with a first and secondbi-stable devices and a switching circuit that activates in a firstphase the first bi-stable device to provide up pulses and the secondbi-stable device to provide down pulses, then, in a second phase,activating the second bi-stable device to provide up pulses and thefirst bi-stable device to provide down pulses to remove mismatch in thepropagation delays of the first and second of bi-stable devices andprovide matched up and down pulse widths.

This invention features a chopped charge pump with matching up and downpulses including a first pair of current sources, a second pair ofcurrent sources, and a switching circuit for switching on in a firstphase, one of each the pair to provide up current pulses and the otherof each pair to provide down current pulses and switching on in a secondphase, the other of each pair to provide up current pulses and the oneof each pair to provide down current pulses to offset error in thecurrent response of the pairs of current sources.

In one embodiment, the first pair of current sources are one polarityand the second pair of current sources are the opposite polarity. Thefirst pair may include P-type devices and the second pair may includeN-type devices. The P-type devices may be PMOS transistors. The N-typedevices may be NMOS transistors. The switching circuit may include aplurality of switching devices responsive to a plurality of enablingsignals for switching on the one of each of the pair and the other ofeach the pair in the first phase and switching on the other of each thepair and the one of each the pair in the second phase.

This invention further features a phase lock loop with zero static phaseoffset including a phase frequency detector responsive to a referencefrequency and a sub-multiple of an output frequency for providing up anddown pulses, a chopped charge pump responsive to the up and down pulsesincluding a first pair of current sources, a second pair of currentsources, and a switching circuit for switching on in a first phase oneof each pair to provide up current pulses and the other of each pair toprovide down current pulses and switching on a second phase the other ofeach pair to provide up current pulses and one of each pair to providedown current pulses to remove mismatch errors in the current response ofeach of the pairs of current sources to eliminate static phase offset. Aloop filter is responsive to the up and down current pulses forproviding differential voltage signals. A differential to single-endedamplifier may be responsive to the differential voltage signals forproviding single-ended voltage signals. A voltage controlled oscillatormay be responsive to the single-ended voltage signals for increasing ordecreasing the output signal frequency and a frequency divider maydivide the output of the voltage controlled oscillator by apredetermined number to generate the sub-multiple of the output signal.

This invention further features a phase lock loop with zero static phaseoffset including a phase frequency detector responsive to a referencefrequency and an output frequency for providing up and down pulses, achopped charge pump responsive to the up and down pulses including afirst pair of current sources, a second pair of current sources, and aswitching circuit for switching on in a first phase one of each pair toprovide up current pulses and the other of each pair to provide downcurrent pulses and switching on a second phase the other of each pair toprovide up current pulses and one of each pair to provide down currentpulses to remove mismatch errors in the current response of each of thepairs of current sources to eliminate static phase offset. A loop filteris responsive to the up and down current pulses for providingdifferential voltage signals. A differential to single-ended amplifiermay be responsive to the differential voltage signals for providingsingle-ended voltage signals and a voltage controlled oscillator may beresponsive to the single-ended voltage signals for increasing ordecreasing the output signal frequency.

This invention also features a chopped phase frequency detector withmatching up and down pulse inputs including first and second bi-stabledevices responsive to a reference frequency and a sub-multiple of anoutput frequency, and a switching circuit for activating in a firstphase the first bi-stable device to provide up pulses and the secondbi-stable device to provide down pulses and activating in a second phasethe second bi-stable device to provide up pulses and the first bi-stabledevice to provide down pulses to remove mismatch in the propagationdelays of the first and second bi-stable devices and provide matched upand down pulse widths.

In one embodiment, the switching circuit may include a plurality ofswitching devices for activating the first and second bi-stable devices.

This invention further features a phase lock loop with zero static phaseoffset including a chopped phase frequency detector including first andsecond bi-stable devices responsive to a reference frequency and asub-multiple of an output frequency, the chopped phase frequencydetector may include a switching circuit for activating in a first phasethe first bi-stable device to provide up pulses and the second bi-stabledevice to provide down pulses and activating in a second phase thesecond bi-stable device to provide up pulses and the first bi-stabledevice to provide down pulses to remove mismatch in the propagationdelays of the first and second bi-stable devices and provide matched upand the down pulse widths. A charge pump is responsive to the up and thedown pulses for providing up and down current pulses. A loop filter isresponsive to the up and down current pulses for providing differentialvoltage signals. A differential to single-ended amplifier may beresponsive to the differential voltage signals and converts thedifferential voltage signals to single-ended voltage signals. A voltagecontrolled oscillator is responsive to the voltage signals forincreasing or decreasing the output signal frequency. A frequencydivider divides the output of the voltage controlled oscillator by apredetermined number to generate the sub-multiple of the output signal.

This invention also features a phase lock loop with zero static phaseoffset including a chopped phase frequency detector including first andsecond bi-stable devices responsive to a reference frequency and asub-multiple of an output frequency. The chopped phase frequencydetector may include a switching circuit for activating in a first phasethe first bi-stable device to provide up pulses and the second bi-stabledevice to provide down pulses and activating in a second phase thesecond bi-stable device to provide up pulses and the first bi-stabledevice to provide down pulses to remove mismatch in the propagationdelays of the first and second bi-stable devices and provide matched theup and the down pulse widths. A chopped charge pump may be responsive tothe up and the down pulses and includes a first pair of current sources,a second pair of current sources, and a switching circuit for switchingon in a first phase one of each pair to provide up current pulses andthe other of each pair to provide down current pulses and switching on asecond phase the other of each pair to provide up current pulses and theone of each pair to provide down current pulses to provide matching upand down current pulses to eliminate static phase offset. A loop filteris responsive to the up and down current pulses for providingdifferential voltage signals. A differential to single-ended amplifiermay be responsive to the differential voltage signals and converts thedifferential voltage signals to single-ended voltage signals. A voltagecontrolled oscillator is responsive to the single-ended voltage signalsfor increasing or decreasing the output signal frequency. A frequencydivider may divide the output of voltage controlled oscillator by apredetermined number to generate the sub-multiple of the output signal.

This invention also features a phase lock loop with zero static phaseoffset including a chopped phase frequency detector including first andsecond bi-stable devices responsive to a reference frequency and anoutput frequency. The chopped phase frequency detector may include aswitching circuit for activating in a first phase the first bi-stabledevice to provide up pulses and the second bi-stable device to providedown pulses and activating in a second phase the second bi-stable deviceto provide up pulses and the first bi-stable device to provide downpulses to remove mismatch in the propagation delays of the first andsecond bi-stable devices and provide matched the up and the down pulsewidths. A chopped charge pump may be responsive to the up and the downpulses and includes a first pair of current sources, a second pair ofcurrent sources, and a switching circuit for switching on in a firstphase one of each pair to provide up current pulses and the other ofeach pair to provide down current pulses and switching on a second phasethe other of each pair to provide up current pulses and the one of eachpair to provide down current pulses to provide matching up and downcurrent pulses to eliminate static phase offset. A loop filter isresponsive to the up and down current pulses for providing differentialvoltage signals. A differential to single-ended amplifier may beresponsive to the differential voltage signals and converts thedifferential voltage signals to single-ended voltage signals and avoltage controlled oscillator is responsive to the single-ended voltagesignals for increasing or decreasing the output signal frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages will occur to those skilled inthe art from the following description of a preferred embodiment and theaccompanying drawings, in which:

FIG. 1 is a schematic block diagram of a typical prior art PLLsynthesizer employing a PFD which generates mismatched up and downpulses and a charge pump which generates mismatched current up andcurrent down pulses;

FIG. 2 is a schematic block diagram of one embodiment of the choppedcharge pump of this invention;

FIG. 3 is a schematic block diagram showing in further detail theswitching devices used to switch the current sources shown in FIG. 2 inthe first phase in accordance with this invention;

FIG. 4 is a timing diagram showing the various enable signals used todrive the switching devices shown in FIG. 3;

FIG. 5 is a schematic block diagram similar to FIG. 3 showing thecurrent sources and switch devices enabled in the second phase inaccordance with this invention;

FIG. 6 is a schematic block diagram of one embodiment of the choppedphase frequency detector with matching up and down pulses of thisinvention; and

FIG. 7 is a schematic block diagram of one embodiment of the phase lockloop synthesizer with zero static phase error of this inventionemploying the chopped phase frequency detector shown in FIG. 6 and thechopped charge pump shown in FIGS. 2, 3, and 5.

DISCLOSURE OF THE PREFERRED EMBODIMENT

Aside from the preferred embodiment or embodiments disclosed below, thisinvention is capable of other embodiments and of being practiced orbeing carried out in various ways. Thus, it is to be understood that theinvention is not limited in its application to the details ofconstruction and the arrangements of components set forth in thefollowing description or illustrated in the drawings.

Prior art PLL synthesizer 10, FIG. 1, typically includes phase frequencydetector (PFD) 12 responsive to a reference frequency signal, f_(REF),on line 14 and a sub-multiple of an output frequency signal, f_(OUT),e.g., n_(DIV) on line 16. Typically n_(DIV) is generated with N-dividercircuit 18 which divides f_(OUT) by N. PFD 12 compares the frequency off_(REF) and N_(DIV) to determine if the frequency of n_(DIV) needs to beincreased or decreased. In order to lock the frequency of n_(DIV) tof_(REF), PFD 12 generates up pulses on line 20 or down pulses on line 22which is applied to charge pump 24. Charge pump 24, generates current upor current down pulses on line 25 which are applied to loop filter 26.Loop filter 26 generates voltages on line 28 which is applied to VCO 30.VCO 30 then increases or decreases the frequency of f_(OUT) on line 31which is input to N-divider circuit 18 to lock the frequency of f_(REF)to n_(DIV). As discussed above, prior art PFD 12 generates up and downpulses which have mismatched pulse widths that result in output phaseoffset and prior art charge pump 24 generates up and down output currentpulses with mismatched magnitudes that also result in output phaseoffset.

In contrast, chopped charge pump 80, FIG. 2 of this invention includesfirst pair 82 of current sources 84 (mp₁) and 86 (mp₂), such as PMOStransistors, that source current out on line 96 to loop filter 99 andsecond pair 88 of current sources 90 (mn₁) and 92 (mn₂), such as NMOStransistors, that sink current in on line 98 from loop filter 101. Thepump up operation increases the differential voltage between line 96(CPO⁺) and line 98 (CPO⁻). Hence, up current is sourced out through line96 (CPO⁺) and sunk into line 98 (CPO⁻). The pump down operationdecreases (makes more negative) the differential voltage between line 96(CPO⁺) and line 98 (CPO⁻). Hence, pump down current is sourced outthrough line 98 (CPO⁻) and sunk into line 96 (CPO⁺).

Switching circuit 94 switches on in a first phase, φ₁, one of first pair82 of current sources and second pair 88 of current sources, e.g.,current source 84 (mp₁) and current source 90 (mp₁) to provide upcurrent pulses on lines 96 and 98 and the other of first pair 82 andsecond pair 84, e.g., current source 86 (mp₂) and current source 92(mn₂) to provide current down pulses on lines 96 and 98. Then, in asecond phase, φ₂, switching circuit 86 switches on the other currentsource of pairs 82 and 84 to provide up and down current pulses, e.g.,current source 86 (mp₂) of pair 82 and current source 92 (mn₂) of pair84 to provide up current and current source 84 (mp₁) of pair 82 andcurrent source 90 (mp₁) of pair 88 to provide down current. Table 1below summarizes the various current sources activated in the first andsecond phases: TABLE 1 φ₁ φ₂ up mp₁ mp₂ mn₁ mn₂ down mp₂ mp₁ mn₂ mn₁

By selectively alternating the up and down current sources which providethe up current and down current pulses matched current up and currentdown pulses are generated by chopped charge pump 80 over two phaseswhich eliminates the corresponding need for compensating static phaseoffset in the PLL.

As discussed above, differential charge pump 80 utilizes a pair of PMOSand NMOS devices to generate up current pulses (e.g., current sources 84and 90) and another pair of PMOS and NMOS devices (e.g., current sources86 and 92) to generate down current pulses. The up versus down mismatchproblem is now significantly reduced because it depends on how a PMOSdevice matches a PMOS device and an NMOS device matches an NMOS device.Utilizing a fully differential architecture of differential charge pump80 with identical up and down current sources reduces the mismatch by atleast an order of magnitude when compared to conventional single-endedcharge pumps. The addition of the chopping technique as described aboveto the differential structure of differential charge pump 80 eliminatesany residual mismatch that may still exist between the two identicalhalves (e.g. one identical half including current sources 84 and 90 andthe one identical half consisting of current sources 86 and 92) ofdifferential charge pump 80 due to process variations. Moreover, thedesign of differential charge pump 80 results in switch charge injectionand output leakage that are both common mode to the differential outputsignal. Because the switches (discussed below) connected to line 96(CPO⁺) are identical in size and layout structure to the switchesconnected to line 98 (CPO⁻), any differential leakage current or chargeinjection component will typically be negligibly small. Moreover,because current sources of identical structure are being chopped themismatch error being chopped is small and thus the spur at the choppingrate will be small. This is a particularly important advantage when usedin a fractional-N PLL using sigma-delta noise shaping because a largespur at the chopping rate would result in quantization noise componentsclose to the chopping frequency being mixed down inside the loopbandwidth.

Switching circuit 94, FIG. 3 typically includes a plurality of switchingdevices, such as switching devices 100, 102, 104, 106, 108, 110, 112,and 114 responsive to a plurality of enabling signals, such as UPn1signal 116, FIG. 4, DNn1 signal 118, UPp1 signal 120, DNp1 signal 122,UPn2 signal 124, DNn2 signal 126, UPp2 signal 128 and DNp2 signal 130.Switching devices 100-114, FIG. 3 are enabled by enabling signals116-130, FIG. 4, as discussed in detail below, to switch current sources84 and 86 of pair 82 and current sources 90 and 92 of pair 88 asdescribed in detail below.

The operation of switching device 80 is explained with reference toFIGS. 3, 4, and 5. In phase φ₁, e.g., when φ₁, signal 133, FIG. 4, ishigh, as indicated at 115, pulse 117 of UPn1 signal 116 enablesswitching device 100, FIG. 3, so that current source 84 generate an upcurrent pulse on line 96, as indicated by arrow 130. Typically φ₁ signal133 is generated with a bi-stable device (not shown), such as a toggleflip-flop clocked at the PFD reference rate or some integer sub-multipleof this rate. This is shown toggling at the reference rate by thefalling edge of f_(REF) signal 111, FIG. 4, (e.g. falling edge 189) withthe rising edges (e.g., rising edges 199, 201 and 203) of f_(REF) signal111 being the active edge at the PFD to generate UPn1 signal 116, DNn1signal 118, UPp1 signal 120, DNp1 signal 122, UPn2 signal 124, DNn2signal 126, UPp2 signal 128 and DNp2 signal 130. φ₁ signal 133 could bederived from any signal at the reference rate as long as it is generatedwith sufficient setup time before the PFD is active and sufficient holdtime after the PFD is active.

Similarly to UPn1 signal 116, pulse 121 of UPp1 signal 120, enablesswitching device 102 so that current source 90 generates an up currentpulse on line 98, as indicated by arrow 132. Similarly, in φ₁, pulse 119of DNn1 signal 118 enables switching device 104 such that current source92 provides a down current pulse on line 96, as indicated by arrow 134.Pulse 123 of DNp1 signal 122 enables switching device 106 so thatcurrent from current source 86 generates a down current pulse on line98, as indicated by arrow 136. In the second phase, φ₂, which is activewhile φ₂ signal 140 is high, as indicated at 141, pulse 125 of UPn2signal 124 enables switching device 112, FIG. 5, so that current source92 generates an up current pulse on line 98, as indicated by arrow 140.φ₂ signal 140 is generated by similar techniques as φ₁ signal 133described above. Similarly, pulse 129 of UPp2 signal 128 enablesswitching device 114 so that current source 86 generates an up currentpulse on line 96, as indicated by arrow 142. Pulse 127 of DNn2 signal126 enables switching device 110 such that current source 90 generates adown current pulse on line 96, as indicated by arrow 144. Finally, pulse131 of DNp2 signal 130 enables switching device 108 so that currentsource 84 generates a down current pulse on line 98, as indicated byarrow 146. The result, over two phases, is that matching up and downcurrent pulses are generated by chopped charge pump 80 which, asdiscussed above, eliminates the need for the PLL to generate a staticphase offset to compensate for charge pump mismatch.

As discussed above, prior art PFDs provide up and down pulses which havemismatched pulse widths which result from mismatch in propagation delaysin both the clock-to-Q delay and reset-to-Q delay paths between the pairof flip-flop devices typically employed in the PFD.

In contrast, chopped phase frequency detector 300, FIG. 6, of thisinvention, with matching up and down pulses, includes first and secondbi-stable devices 304 and 306, e.g., D-type flip-flops, responsive toinput reference signal f_(REF) on line 308 and a sub-multiple of theoutput signal n_(DIV) on line 310. Switching circuit 311 switches on inthe first phase, φ₁, switches 312 and 314 which routes the referencesignal, f_(REF) on line 308 to bi-stable device 304 to provide up pulseson line 318 and routes the sub-multiple of the reference signal,N_(DIV), on line 310 to bi-stable device 306 to provide down pulses online 320. Switching device 311 then switches on in the second phase, φ₂,switches 316 and 318 to route the reference signal, f_(REF) on line 308to bi-stable device 306 to provide up pulses on line 320 and routes thesub-multiple of the reference signal, N_(DIV), on line 310 to bi-stabledevice 304 to provide down pulses on line 318. Phases φ₁ and φ₂ aregenerated similar to φ₁ phase signal 133, FIG. 4, and φ₂ signal 140.

The result is that chopped phase frequency detector 320 provides matchedtotal up and total down pulse widths over two phases. This removes theproblems associated with mismatch in propagation delays in the first ofbi-stable devices 304 and 306 and results in zero output offset.

Phase lock loop 400, FIG. 7, of this invention with zero static phaseerror, includes chopped phase frequency detector 402 of similar designas chopped phase frequency detector of this invention as describedabove, responsive to a reference frequency signal, f_(REF), on line 404and a sub-multiple of an output frequency signal, f_(out), e.g., n_(DIV)on line 406. The sub-multiple of the output frequency signal, f_(OUT),may be an integer sub-multiple or a fractional sub-multiple. Asdiscussed above, chopped PFD 402 provides matched up and down pulseswith matched pulse widths on lines 410 and 412 with zero output offsetwhich are applied to chopped charge pump 414, of similar design as thechopped charge pump of this invention, described above. Chopped chargepump 414 generates a matched current up and current down pulse over twophases on lines 420 and 422. Both of these improvements dynamicallyeliminate mismatch through chopping, and eliminate the need for the PLLto develop a static phase offset. Loop filter 426 is responsive to thematched current up and current down pulses to generate voltages on lines428 and 430 which are applied to differential to single-ended amplifier432 which converts the differential voltage between lines 428 and 430 toa single-ended voltage on line 434 which is applied to VCO 430. Furtherdetails regarding the use of a differential charge pump, and convertingthe differential voltages generated by the loop filter to a single-endedvoltage are disclosed in co-pending application filed on an even dateherewith by the inventive entity hereof entitled “Differential ChargePump Phase Lock Loop (PLL) Synthesizer with Adjustable Tuning VoltageRange”. VCO 430 increases or decreases the frequency of f_(OUT) on line432 which is input to N-divider circuit 434 in order to lock thefrequency of f_(REF) _(to n) _(DIV). Although in this example, phaselock loop 400 includes chopped phase frequency detector 402 and choppedcharge pump 414, this is not a necessary limitation of this invention,as phase lock loop 400 may include chopped charge pump 414 with aconventional phase frequency detector or chopped phase frequencydetector 402 with a conventional differential charge pump.

Although specific features of the invention are shown in some drawingsand not in others, this is for convenience only as each feature may becombined with any or all of the other features in accordance with theinvention. The words “including”, “comprising”, “having”, and “with” asused herein are to be interpreted broadly and comprehensively and arenot limited to any physical interconnection. Moreover, any embodimentsdisclosed in the subject application are not to be taken as the onlypossible embodiments.

Other embodiments will occur to those skilled in the art and are withinthe following claims:

1. A chopped charge pump with matching up and down pulses comprising: afirst pair of current sources; a second pair of current sources; and aswitching circuit for switching on in a first phase one of each saidpair to provide up current pulses and the other of each said pair toprovide down current pulses and switching on in a second phase saidother of each said pair to provide up current pulses and said one ofeach said pair to provide down current pulses to remove mismatch errorsin the current response of each said pairs of current sources.
 2. Thechopped charge pump of claim 1 in which said first pair of currentsources are one polarity and said second pair of current sources are theopposite polarity.
 3. The chopped charge pump of claim 1 in which saidfirst pair includes P-type devices and said second pair includes N-typedevices.
 4. The chopped charge pump of claim 3 in which said P-typedevices are PMOS transistors.
 5. The chopped charge pump of claim 3 inwhich said N-type devices are NMOS transistors.
 6. The chopped chargepump of claim 6 in which said switching circuit includes a plurality ofswitching devices responsive to a plurality of enabling signals forswitching on said one of each said pair and said other of each said pairin said first phase and switching on said other of each said pair andsaid one of each said pair in said second phase.
 7. A phase lock loopwith zero static phase offset comprising: a phase detector circuitresponsive to a reference frequency and a sub-multiple of an outputfrequency for generating up and down pulses; a chopped charge pumpresponsive to said up and down pulses including: a first pair of currentsources; a second pair of current sources; and a switching circuit forswitching on in a first phase one of each said pair to provide upcurrent pulses and the other of each said pair to provide down currentpulses and switching on in a second phase said other of each said pairto provide up current pulses and said one of each said pair to providedown current pulses to provide matching up and down current pulses toremove mismatch errors in the current response of each of said pairs ofcurrent sources to eliminate static phase offset; a loop filterresponsive to said up and down current pulses for providing differentialvoltage signals; a differential to single-ended amplifier responsive tosaid differential voltage signals for providing sing-ended voltagesignals; a voltage controlled oscillator responsive to said voltagesignals for increasing or decreasing said output signal frequency; and afrequency divider for dividing the output of said voltage controlledoscillator by a predetermined number to generate said sub-multiple ofsaid output signal.
 8. A phase lock loop with zero static phase offsetcomprising: a phase detector circuit responsive to a reference frequencyand an output frequency for generating up and down pulses; a choppedcharge pump responsive to said up and down pulses including: a firstpair of current sources; a second pair of current sources; and aswitching circuit for switching on in a first phase one of each saidpair to provide up current pulses and the other of each said pair toprovide down current pulses and switching on in a second phase saidother of each said pair to provide up current pulses and said one ofeach said pair to provide down current pulses to provide matching up anddown current pulses to remove mismatch errors in the current response ofeach of said pairs of current sources to eliminate static phase offset;a loop filter responsive to said up and down current pulses forproviding differential voltage signals; a differential to single-endedamplifier responsive to said differential voltage signals for providingsing-ended voltage signals; and a voltage controlled oscillatorresponsive to said voltage signals for increasing or decreasing saidoutput signal frequency.
 9. A chopped phase frequency detector withmatching up and down pulses comprising: first and second bi-stabledevices responsive to a reference frequency and a sub-multiple of anoutput frequency; and a switching circuit for activating in a firstphase said first bi-stable device to provide up pulses and said secondbi-stable device to provide down pulses and activating in a second phasesaid second bi-stable device to provide up pulses and said firstbi-stable device to provide down pulses to remove mismatch inpropagation delays of said first and second bi-stable devices andprovide matched up and down pulse widths.
 10. The chopped frequencydetector of claim 9 in which said switching circuit includes a pluralityof switching devices for activating said first and second bi-stabledevices.
 11. A phase lock loop with zero static phase offset comprising:a chopped phase frequency detector including a first and second ofbi-stable devices responsive to a reference frequency and a sub-multipleof an output frequency, said chopped phase frequency detector includinga switching circuit for activating in a first phase said first bi-stabledevice to provide up pulses and said second bi-stable device to providedown pulses and activating in a second phase the said second bi-stabledevice to provide up pulses and said first bi-stable device to providedown pulses to remove mismatch in propagation delays of said first andsecond bi-stable devices and provide matched up and down pulse widths; acharge pump responsive to said matched up and said down pulses forproviding up and down current pulses; a loop filter responsive to saidup and down current pulses for providing differential voltage signals; adifferential to single-ended amplifier responsive to said differentialvoltage signals for providing a single-ended voltage signal; a voltagecontrolled oscillator responsive to said voltage signal for increasingor decreasing said output signal frequency; and a frequency divider fordividing the output of said voltage controlled oscillator by apredetermined number to generate said sub-multiple of said outputsignal.
 12. A phase lock loop with zero static phase offset comprising:a chopped phase frequency detector including a first and second ofbi-stable devices responsive to a reference frequency and a sub-multipleof an output frequency, said chopped phase frequency detector includinga switching circuit for activating in a first phase said first bi-stabledevice to provide up pulses and said second bi-stable device to providedown pulses and activating in a second phase the said second bi-stabledevice to provide up pulses and said first bi-stable device to providedown pulses to remove mismatch in propagation delays of said pair ofbi-stable devices and provide matched up and down pulse widths; achopped charge pump responsive to said up and said down pulsesincluding: a first pair of current sources; a second pair of currentsources; and a switching circuit for switching on in a first phase oneof each said pair to provide up current pulses and the other of eachsaid pair to provide down current pulses and switching on in a secondphase said other of each said pair to provide up current pulses and saidone of each said pair to provide down current pulses to provide matchingup and down current pulses to remove mismatch errors in the currentresponse of said pairs of current sources to eliminate static phaseoffset; a loop filter responsive to said up and down current pulses forproviding voltage signals; a differential to single-ended amplifierresponsive to said differential voltage signals for providing asingle-ended voltage signal; a voltage controlled oscillator responsiveto said single-ended voltage signal for increasing or decreasing saidoutput signal frequency; and a frequency divider for dividing the outputof said voltage controlled oscillator by a predetermined number togenerate said sub-multiple of said output signal.
 13. A phase lock loopwith zero static phase offset comprising: a chopped phase frequencydetector including a first and second of bi-stable devices responsive toa reference frequency and an output frequency, said chopped phasefrequency detector including a switching circuit for activating in afirst phase said first bi-stable device to provide up pulses and saidsecond bi-stable device to provide down pulses and activating in asecond phase the said second bi-stable device to provide up pulses andsaid first bi-stable device to provide down pulses to remove mismatch inpropagation delays of said pair of bi-stable devices and provide matchedup and down pulse widths; a chopped charge pump responsive to said upand said down pulses including: a first pair of current sources; asecond pair of current sources; and a switching circuit for switching onin a first phase one of each said pair to provide up current pulses andthe other of each said pair to provide down current pulses and switchingon in a second phase said other of each said pair to provide up currentpulses and said one of each said pair to provide down current pulses toprovide matching up and down current pulses to remove mismatch errors inthe current response of said pairs of current sources to eliminatestatic phase offset; a loop filter responsive to said up and downcurrent pulses for providing voltage signals; a differential tosingle-ended amplifier responsive to said differential voltage signalsfor providing a single-ended voltage signal; and a voltage controlledoscillator responsive to said single-ended voltage signal for increasingor decreasing said output signal frequency.